View 5PB1104CMGI8_8776416.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

datasheet 5pb11xx may 13, 2016 1 ?2016 integrated device technology, inc. 1.8v to 3.3v lvcmos high performance clock buffer family 5pb11xx description the 5pb11xx is a high-performance lvcmos clock buffer family. it has best-in-class additive phase jitter of 50fsec rms. there are five different fan-out variations, 1:2 to 1:10, available. the idt5pb11xx also supports a synchronous glitch-free output enable function to eliminate any potential intermediate incorrect output clock cycles when enabling or disabling outputs. it comes in various packages and can operate from a 1.8v to 3.3v supply. features ? high performance 1:2, 1:4, 1: 6, 1:8, 1:10 lvcmos clock buffer ? very low pin-to-pin skew <50 ps ? very low additive jitter <50 fs ? supply voltage: 1.8v to 3.3v ? f max = 200mhz ? integrated serial termination for 50ohm channel ? packaged in 8-, 14-, 16-, 20-pin tssop and small dfn and qfn packages ? extended (-40c to +105c) temperature range block diagram lvcmos y0 clkin y1 y2 y3 lvcmos lvcmos lvcmos lvcmos lvcmos yn 1g
1.8v to 3.3v lvcmos high perform ance clock buffer family 2 may 13, 2016 5pb11xx datasheet pin assignments for tssop packages pin descriptions for tssop packages device number lvcmos clock input clock output enable lvcmos clock output supply voltage ground clkin 1g y0, y1, . . . y9 v dd gnd 5pb1102pggi 1 2 3, 8 6 4 5pb1104pggi 1 2 3, 8, 5, 7 6 4 5pb1106pggi 1 2 3, 14, 11, 13, 6, 9 5, 8, 12 4, 7, 10 5pb1108pggi 1 2 3, 16, 13, 15, 6, 11, 8, 9 5, 10, 14 4, 7, 12 5pb1110pggi 1 2 3, 20, 17, 19, 6, 15, 8, 13, 12, 10 5, 9, 14, 18 4, 7, 11, 16 clkin 1 2 3 45 6 7 8 1g y0 gnd nc vdd nc y1 5pb1102pggi clkin 1 2 3 45 6 7 8 1g y0 gnd y2 vdd y3 y1 5pb1104pggi clkin 1 2 3 4 5 6 78 9 10 11 12 13 14 1g y0 gnd vdd y4 gnd vdd y5 gnd y2 vdd y3 y1 5pb1106pggi clkin 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 1g y0 gnd vdd y4 gnd y6 y7 vdd y5 gnd y2 vdd y3 y1 5pb1108pggi clkin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1g y0 gnd vdd y4 gnd y6 vdd y9 gnd y8 y7 vdd y5 gnd y2 vdd y3 y1 5pb1110pggi
may 13, 2016 3 1.8v to 3.3v lvcmos high performance clock buffer family 5pb11xx datasheet pin assignments for dfn/qfn packages pin descriptions for dfn/qfn packages output logic table after at least three cycles of input clock toggling. output en able function is asynchronous to eliminate any intermediate incor rect output clock cycles durin g transition which may cause frequency peaking to the downstream device. device number lvcmos clock input clock output enable lvcmos clock output supply voltage ground clkin 1g y0, y1, . . . y9 v dd gnd 5pb1102cmgi 1 2 3, 8 6 4 5pb1104cmgi 1 2 3, 5, 7, 8 6 4 5pb1106cmgi 15 16 1, 4, 9, 11, 13, 14 3, 8, 12 2, 5, 10 5pb1108cmgi 15 16 1, 4, 6, 7, 9, 11, 13, 14 3, 8, 12 2, 5, 10 5pb1110ndgi 19 20 1, 4, 6, 8, 10, 11, 13 , 15, 17, 18 3, 7, 12, 16 2, 5, 9, 14 inputs output clkin 1g yn xll lhl hhh clkin 1 2 3 45 6 7 8 1g y0 gnd nc vdd nc y1 5pb1102cmgi clkin 1 2 3 45 6 7 8 1g y0 gnd y2 vdd y3 y1 5pb1104cmgi clkin 1 2 3 4 5 678 9 10 11 12 13 14 15 16 1g y0 gnd vdd y4 gnd nc y5 vdd y2 gnd vdd y3 y1 5pb1106cmgi nc clkin 1 2 3 4 5 678 9 10 11 12 13 14 15 16 1g y0 gnd vdd y4 gnd y6 y5 vdd y2 gnd vdd y3 y1 5pb1108cmgi y7 clkin 1 2 3 4 5 678910 11 12 13 14 15 16 17 18 19 20 1g y0 gnd vdd y4 gnd y6 vdd y9 gnd y8 y7 vdd y5 gnd y2 vdd y3 y1 5pb1110ndgi
1.8v to 3.3v lvcmos high perform ance clock buffer family 4 may 13, 2016 5pb11xx datasheet absolute maximum ratings stresses above the ratings listed below can cause permanent dama ge to the 5pb11xx. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. function al operation of the device at these or any other conditions above those indicated in the operational sections of the specif ications is not implied. exposur e to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics (vdd = 1.8v, 2.5v, 3.3v) vdd=1.8v 5% , ambient temperature -40 to +105c, unless stated otherwise notes: 1. nominal switch ing threshold is vdd/2 item rating supply voltage, vdd 3.465v output enable and all outputs -0.4 v to vdd+0.5 v clkin -0.4 v to 3.465v ambient operating temperature (extended) -40 to +105 ? c storage temperature -65 to +150 ? c junction temperature 125 ? c soldering temperature 260 ? c parameter min. typ. max. units ambient operating temperature (extended) -40 +105 ? c power supply voltage (measured in respect to gnd) +1.71 +3.465 v parameter symbol conditions min. typ. max. units operating voltage vdd 1.71 1.89 v input high voltage, clkin v ih note 1 0.7xvdd vdd v input low voltage, clkin v il note 1 0.3xvdd v input high voltage, 1g v ih 1.6 vdd v input low voltage, 1g v il 0.6 v output high voltage v oh i oh = -5 ma 1.4 v output low voltage v ol i ol = 5 ma 0.4 v nominal output impedance z o 50 ? input capacitance c in clkin, 1g pin 5 pf operating supply current 5pb1102 idd 100mhz, no load, 25c 8 ma 5pb1104 100mhz, no load, 25c 12 5pb1106 100mhz, no load, 25c 16 5pb1108 100mhz, no load, 25c 21 5pb1110 100mhz, no load, 25c 25
may 13, 2016 5 1.8v to 3.3v lvcmos high performance clock buffer family 5pb11xx datasheet vdd=2.5 v 5% , ambient temperature -40 to +105c, unless stated otherwise vdd=3.3 v 5% , ambient temperature -40 to +105c, unless stated otherwise parameter symbol conditions min. typ. max. units operating voltage vdd 2.375 2.625 v input high voltage, clkin v ih note 1 0.7xvdd vdd v input low voltage, clkin v il note 1 0.3xvdd v input high voltage, 1g v ih 1.8 vdd v input low voltage, 1g v il 0.7 v output high voltage v oh i oh = -8 ma 1.9 v output low voltage v ol i ol = 8 ma 0.5 v nominal output impedance z o 50 ? input capacitance c in clkin, 1g pin 5 pf operating supply current 5pb1102 idd 100mhz, no load, 25c 10 ma 5pb1104 100mhz, no load, 25c 15 5pb1106 100mhz, no load, 25c 22 5pb1108 100mhz, no load, 25c 28 5pb1110 100mhz, no load, 25c 33 parameter symbol conditions min. typ. max. units operating voltage vdd 3.135 3.465 v input high voltage, clkin v ih note 1 0.7xvdd vdd v input low voltage, clkin v il note 1 0.3xvdd v input high voltage, 1g v ih 2vddv input low voltage, 1g v il 0.8 v output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = 12 ma 0.7 v nominal output impedance z o 50 ? input capacitance c in clkin, 1g pin 5 pf operating supply current 5pb1102 idd 100mhz, no load, 25c 12 ma 5pb1104 100mhz, no load, 25c 20 5pb1106 100mhz, no load, 25c 25 5pb1108 100mhz, no load, 25c 35 5pb1110 100mhz, no load, 25c 40
1.8v to 3.3v lvcmos high perform ance clock buffer family 6 may 13, 2016 5pb11xx datasheet ac electrical characteristics (vdd = 1.8v, 2.5v, 3.3v) vdd = 1.8v 5% , ambient temperature -40 to +105c, unless stated otherwise vdd = 2.5 v 5% , ambient temperature -40 to +105c, unless stated otherwise vdd = 3.3 v 5% , ambient temperature -40 to +105c, unless stated otherwise parameter symbol conditions min. typ. max. units input frequency 0200mhz output rise time (2 pf load) t or 0.36v to 1.44v, c l =2 pf 0.5 0.75 ns output fall time (2 pf load) t of 1.44v to 0.36v, c l =2 pf 0.5 0.75 ns output rise time (5 pf load) t or 0.36v to 1.44v, c l =5 pf 0.8 1.0 ns output fall time (5 pf load) t of 1.44v to 0.36v, c l =5 pf 0.8 1.0 ns start-up time t start-up part start-up time for valid outputs after vdd ramp-up 3 ms propagation delay note 1 1.9 2.2 ns buffer additive phase jitter, rms 156.25 mhz, integration range: 12khz-20mhz 0.05 ps output to output skew (5pb1102/04/06) rising edges at vdd/2, note 2 35 50 ps output to output skew (5pb1108/10) ris ing edges at vdd/2, note 2 45 65 ps device to device skew rising edges at vdd/2 200 ps output enable time t en c l < 5 pf 3 cycles output disable time t dis c l < 5 pf 3 cycles parameter symbol conditions min. typ. max. units input frequency 0200mhz output rise time (2 pf load) t or 0.5v to 2.0v, c l =2 pf 0.4 0.7 ns output fall time (2 pf load) t of 2.0v to 0.5v, c l =2 pf 0.4 0.7 ns output rise time (5 pf load) t or 0.5v to 2.0v, c l =5 pf 0.75 1.0 ns output fall time (5 pf load) t of 2.0v to 0.5v, c l =5 pf 0.75 1.0 ns start-up time t start-up part start-up time for valid outputs after vdd ramp-up 3 ms propagation delay note 1 2.4 2.9 ns buffer additive phase jitter, rms 156.25 mhz, integration range: 12khz-20mhz 0.05 ps output to output skew (5pb1102/04/06) rising edges at vdd/2, note 2 35 50 ps output to output skew (5pb1108/10) ris ing edges at vdd/2, note 2 45 65 ps device to device skew rising edges at vdd/2 200 ps output enable time t en c l < 5 pf 3 cycles output disable time t dis c l < 5 pf 3 cycles parameter symbol conditions min. typ. max. units input frequency 0200mhz output rise time (2 pf load) t or 0.66v to 2.64v, c l =2 pf 0.45 0.6 ns output fall time (2 pf load) t of 2.64v to 0.66v, c l =2 pf 0.45 0.6 ns output rise time (5 pf load) t or 0.66v to 2.64v, c l = 5pf 0.7 1.0 ns output fall time (5 pf load) t of 2.64v to 0.66v, c l =5 pf 0.7 1.0 ns start-up time t start-up part start-up time for valid outputs after vdd ramp-up 3 ms propagation delay note 1 2 2.4 ns buffer additive phase jitter, rms 156.25 mhz, integration range: 12khz-20mhz 0.05 ps output to output skew (5pb1102/04/06) rising edges at vdd/2, note 2 35 50 ps
may 13, 2016 7 1.8v to 3.3v lvcmos high performance clock buffer family 5pb11xx datasheet notes: 1. with rail to rail input clock 2. between any 2 outputs with equal loading. 3. duty cycle on outputs will match incoming clock duty c ycle. consult idt for tight duty cycle clock generators. phase noise plots the phase noise plots above show the low additive jitter of th e 5pb11xx high-performance buffer. with an integration range of 12khz to 20mhz, the reference input has about 58.9fs of rms pha se jitter while the output of 5 pb11xx has about 70.9fs of rms phase jitter. this results in a low additive phase jitter of only 39fs. test load and circuit output to output skew (5pb1108/10) ris ing edges at vdd/2, note 2 45 65 ps device to device skew rising edges at vdd/2 200 ps output enable time t en c l < 5 pf 3 cycles output disable time t dis c l < 5 pf 3 cycles parameter symbol conditions min. typ. max. units figure 1. 5pb11xx reference phase noise 58.9fs (12khz to 20mhz) figure 2. 5pb11xx output phase noise 70.9fs (12khz to 20mhz) 5 i n c h e s cl = 5pf 50ohms
1.8v to 3.3v lvcmos high perform ance clock buffer family 8 may 13, 2016 5pb11xx datasheet marking diagrams notes: 1. ?aa? denotes the last two digits of the part number for 8-pin tssop and dfn (e.g. 02, 04). 2. ? ** ? is the lot sequence. 3. ?xxx? denotes the last three characters of the asm lot (20-pin qfn only). 4. ?yyww?, ?yww?, ?yw?, or ?y? is th e last digit(s) of the year and week that the part was assembled. 5. ?$? denotes the mark code. 6. ?g? after the two-letter package code denotes rohs compliant package. 7. ?i? denotes extended temperature range device. 8. bottom marking: country of origin (tssop only). yww$ b11aai 8-pin tssop idt5pb11 06pggi yyww$ 14-pin tssop idt5pb11 08pggi yyww$ 16-pin tssop idt5pb11 10pggi yyww$ 20-pin tssop 11aa yw** 8-pin dfn xxx yww$ 110i 20-pin qfn 1106 y** 16-pin qfn 1108 y** 16-pin qfn
may 13, 2016 9 1.8v to 3.3v lvcmos high performance clock buffer family 5pb11xx datasheet package outline and package dimensions (8-pin dfn, 2mm x 2 mm body, 0.5mm pitch)
1.8v to 3.3v lvcmos high performan ce clock buffer family 10 may 13, 2016 5pb11xx datasheet package outline and pack age dimensions, cont. (8-pin dfn, 2mm x 2mm body, 0.5mm pitch)
may 13, 2016 11 1.8v to 3.3v lvcmos high performance clock buffer family 5pb11xx datasheet package outline and package dimensions (16-pin qfn, 2.5mm x 2. 5mm body, 0.4mm pitch)
1.8v to 3.3v lvcmos high performan ce clock buffer family 12 may 13, 2016 5pb11xx datasheet package outline and pack age dimensions, cont. (16-pin qfn, 2.5mm x 2.5mm body, 0.4mm pitch)
may 13, 2016 13 1.8v to 3.3v lvcmos high performance clock buffer family 5pb11xx datasheet package outline and package dimensions (20-pin qfn, 3mm x 3mm body, 0.4mm pitch)
1.8v to 3.3v lvcmos high performan ce clock buffer family 14 may 13, 2016 5pb11xx datasheet package outline and pack age dimensions, cont. (20-pin qfn, 3mm x 3 mm body, 0.4mm pitch)
may 13, 2016 15 1.8v to 3.3v lvcmos high performance clock buffer family 5pb11xx datasheet package outline and package dimensions (8-, 14-, 16-, 20-pin tssop)
1.8v to 3.3v lvcmos high performan ce clock buffer family 16 may 13, 2016 5pb11xx datasheet package outline and pack age dimensions, cont. (8-, 14-, 16-, 20-pin tssop)
may 13, 2016 17 1.8v to 3.3v lvcmos high performance clock buffer family 5pb11xx datasheet package outline and pack age dimensions, cont. (8-, 14-, 16-, 20-pin tssop)
1.8v to 3.3v lvcmos high performan ce clock buffer family 18 may 13, 2016 5pb11xx datasheet ordering information ?g? after the two-letter package code denotes pb-free configuration, rohs compliant. revision history part / order number marking shippi ng packaging package temperature 5pb1102pggi see page 8 tubes 8-pin tssop -40 to +105 ? c 5pb1102pggi8 tape and reel 8-pin tssop -40 to +105 ? c 5pb1104pggi tubes 8-pin tssop -40 to +105 ? c 5pb1104pggi8 tape and reel 8-pin tssop -40 to +105 ? c 5pb1106pggi tubes 14-pin tssop -40 to +105 ? c 5pb1106pggi8 tape and reel 14-pin tssop -40 to +105 ? c 5pb1108pggi tubes 16-pin tssop -40 to +105 ? c 5pb1108pggi8 tape and reel 16-pin tssop -40 to +105 ? c 5pb1110pggi tubes 20-pin tssop -40 to +105 ? c 5pb1110pggi8 tape and reel 20-pin tssop -40 to +105 ? c 5pb1102cmgi cut tape 8-pin dfn -40 to +105 ? c 5pb1102cmgi8 tape and reel 8-pin dfn -40 to +105 ? c 5pb1104cmgi cut tape 8-pin dfn -40 to +105 ? c 5PB1104CMGI8 tape and reel 8-pin dfn -40 to +105 ? c 5pb1104cmgi/w tape and reel 8-pin dfn -40 to +105 ? c 5pb1106cmgi cut tape 16-pin qfn -40 to +105 ? c 5pb1106cmgi8 tape and reel 16-pin qfn -40 to +105 ? c 5pb1108cmgi cut tape 16-pin qfn -40 to +105 ? c 5pb1108cmgi8 tape and reel 16-pin qfn -40 to +105 ? c 5pb1110ndgi tubes 20-pin qfn -40 to +105 ? c 5pb1110ndgi8 tape and reel 20-pin qfn -40 to +105 ? c rev. date originator description of change a 03/20/15 b. chandhoke initial release. b 05/19/15 b. chandhoke 1. expanded output enable function text in general description, and within the note under "output logic table". 2. updated all "buffer additive phase jitter, rms" conditions from 125mhz to 156.25mhz. c 06/09/15 b. chandhoke 1. corrected typos in part numbers in dc electrical tables. 2. updated existing output rise/fall time specs for 5pf load. 3. added additional output rise/fall specs for 2 pf load. d 06/15/15 b. chandhoke fixed typos in output rise/fall time 5pf specs for cl conditions; should be 5pf; not 2pf. e 06/22/15 b. chandhoke changed 3.3v operating voltage spec from 3.15 min to 3.135 min; 3.45 max to 3.465 max. f 08/24/15 b. chandhoke 1. added 5pb1104cmgi w orderable part. 2. updated abs max ratings table for ?output enable and all outputs? and ?clkin?; changed -0.5 v to -0.4 and added -0.4 to... respectively. g 05/13/16 h.g. replace ndg20 po d drawing with latest version.
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications d escribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfun ction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2016 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

▲Up To Search▲

Price & Availability of 5PB1104CMGI8

	To Download 5PB1104CMGI8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .